1. Field of the Invention
The present invention relates to an electrostatic protection circuit, and more particularly, to a protection circuit against electrostatic discharge (ESD) flowing from external terminals.
2. Description of the Related Art
A semiconductor integrated circuit (IC) device including MOS transistors requires an ESD tolerance against a surge voltage and a surge current which are applied to external terminals (input and output pads) of the semiconductor integrated circuit device by electrostatic discharge. Therefore, electrostatic protection circuits are normally connected with the external terminals. One of the electrostatic protection circuits to be used is a protection element including an NMOS transistor whose gate is grounded.
In recent years, along with a reduction in size of the semiconductor integrated circuit device, the tolerances of internal transistors against electrostatic discharge have become increasingly important. FIG. 10 shows the dependences of a breakdown voltage (VBD) of a gate oxide film and a clamp voltage (Vclamp) of a protection element on a gate oxide thickness. In FIG. 10, along with the reduction in transistor size, the gate oxide film becomes thinner and VBD rapidly reduces in substantially proportional to the thickness of the gate oxide film. In contrast to this, Vclamp of an NMOS type protection element whose gate is grounded does not substantially reduce, so a design window (VBD-Vclamp) indicating the ESD tolerance becomes smaller.
In order to extend the design window, it has been known that a sub-protection element is further provided for an element to be protected. The sub-protection element further reduces an electrostatic discharge voltage applied to the element to be protected, which leads to the extension of the design window. The main protection element handles a large electrostatic discharge current. In most case, an electrostatic discharge voltage can not be completely eliminated by the main protection element. The sub-protection element further reduces the electrostatic discharge voltage applied to the element to be protected, not to be completely eliminated by the main protection element.
An example of such an electrostatic protection circuit is described in AJITH AMERASEKERA, “ESD in Silicon Integrated Circuits”, Second Edition, WILEY, 2002, pp. 117-118 (see FIG. 11). In FIG. 11, an electrostatic protection element 100a is provided between an input terminal In and a ground terminal GND and an electrostatic protection element 100b is provided between the input terminal In and a power supply terminal VDD. A resistor element R101 is provided between the input terminal In and a connection point between a gate of an Nch transistor N101 and a gate of a Pch transistor P101. A protection element 101, for example, an Nch transistor N102 whose drain is connected with the two gates and whose gate and source are connected with the ground terminal GND is provided between the connection point between the two gates and the ground terminal GND. The Nch transistor N101 and the Pch transistor P101 serve as an input stage driver (inverter circuit) and transfer a signal supplied to the input terminal In to an internal circuit.
In the electrostatic protection circuit having the structure as described above, each of the electrostatic protection elements 100a and 100b acts as the main protection element and the resistor element R101 and the protection element 101 act as the sub-protection element. The input stage driver corresponds to the element to be protected. That is, when a voltage VESD caused by electrostatic discharge is applied to the input terminal In, a discharge current Id which cannot be absorbed by the electrostatic protection element 100a flows into the ground terminal GND through the resistor element R101 and the protection element 101 (Nch transistor N102 which is broken down). At this time, a source-gate voltage Vstress of the Nch transistor N101 is alleviated by a breakdown voltage of the Nch transistor N102, thereby preventing the Nch transistor N101 from being damaged by electrostatic discharge.
Another example of the electrostatic protection circuit is described in US 2005/0231866 A (see FIG. 12). In FIG. 12, an electrostatic protection element 206 is provided between an input terminal In and a ground terminal VSS and an electrostatic protection element 208 is provided between the input terminal In and a power supply terminal VDD. An electrostatic protection element 226 is provided between the input terminal In (that is, a connection point between a gate of an Nch transistor 204 and a gate of a Pch transistor 202) and a source of the Nch transistor 204. An electrostatic protection element 228 is provided between the input terminal In and a source of the Pch transistor 202. An impedance circuit 224 such as a resistor element is provided between the source of the Nch transistor 204 and the ground terminal VSS. An impedance circuit 222 such as a resistor element is provided between the source of the Pch transistor 202 and the power supply terminal VDD. The Nch transistor 204 and the Pch transistor 202 serve as an input stage driver (inverter circuit) and transfer a signal supplied to the input terminal In to an output terminal OUTPUT.
In the electrostatic protection circuit having the structure as described above, each of the electrostatic protection elements 206 and 208 acts as the main protection element. A combination of the electrostatic protection element 226 and the impedance circuit 224 and a combination of the electrostatic protection element 228 and the impedance circuit 222 act as the sub-protection element. The input stage driver corresponds to the element to be protected. That is, when a voltage Vesd caused by electrostatic discharge is applied to the input terminal In, a discharge current which cannot be absorbed by the electrostatic protection element 206 flows into the ground terminal VSS through the electrostatic protection element 226 and the impedance circuit 224. At this time, a source-gate voltage of the Nch transistor 204 is alleviated by a breakdown voltage Vasp of the electrostatic protection element 226, thereby preventing the Nch transistor 204 from being damaged by electrostatic discharge. The electrostatic protection circuit performs the same electrostatic protection operation even on the Pch transistor 202, so the description thereof is omitted here.
According to the conventional electrostatic protection circuit, when the voltage caused by electrostatic discharge is applied to the input terminal, the discharge current which cannot be absorbed by the main protection element flows into the ground terminal (or the power supply terminal) through the sub-protection element and the impedance circuit (which corresponds to the resistor element R101 in the case of AJITH AMERASEKERA, “ESD in Silicon Integrated Circuits”, Second Edition, WILEY, 2002, pp. 117-118 or corresponds to the impedance circuit 224 in the case of US 2005/0231866 A). Therefore, the source-gate voltage of the Nch transistor (Pch transistor) of the input stage driver is alleviated, so the Nch transistor (Pch transistor) can be prevented from being damaged. In the electrostatic protection circuit, a normal signal inputted from the input terminal is not affected by the sub-protection element because the sub-protection element itself is maintained at high impedance.
However, it is liable to adversely affect the normal signal inputted from the input terminal by the impedance circuit. For example, in the case of FIG. 11, the resistor element R101 and a parasitic capacitor formed between the source and drain of the Nch transistor N102 serve as a low-pass filter, thereby cutting off a high frequency component of the signal. In the case of FIG. 12, an amplitude voltage (dynamic range) of an output signal is narrowed by the impedance circuit 224 (222).